1. Field of the Invention
The present invention relates to a frequency multiplier for controlling a pulse width, and in particular, to a frequency multiplier for controlling a pulse width that maintains a prescribed pulse width.
2. Background of the Related Art
FIG. 1 illustrates a related art frequency multiplier. Delay units D1, . . . , DN delay respectively an input signal VI at different delay ratios, and a multiplexor 1 selectively outputs a corresponding one of delay speeds TD 1, . . ., TD N of the delay units D1, . . . , DN. An exclusive OR-gate 2 exclusively ORs an output signal from the multiplexor 1 and the input signal VI.
The delay units D ,. . ., DN having different delay ratios delay the input signal VI to output delayed signals having the delay speeds TD 1,. . ., TD N to the multiplexor 1. The multiplexor 1 selects one of the delay speeds TD1, . . ., TD N of the delay units D1, . . . DN and outputs the delay speed. The OR-gate 2 exclusively ORs the output signal from the multiplexor 1 and the input signal VI.
Therefore, an output signal VO from the exclusive OR-gate 2 has a different pulse width based on the delay ratios of the delay units D1, . . . , DN. However, the related art frequency multiplier has various disadvantages. The related art frequency multiplier uses a plurality of delay devices. In addition, an accurate delay ratio is required for the delay units to maintain the pulse width having a predetermined range. If the delay ratio of the delay device varies based on semiconductor fabrication process variations, it is not possible to maintain the pulse width within the predetermined range.